(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to an optical lithographic exposure apparatus with a multiple mask capability suitable for double-exposure processes in the manufacture of integrated circuits.
(2) Description of the Prior Art
As optical lithography is used to delineate 0.1 micron and smaller features, the lithographic tools must work in a low k1 region. The k1, or Rayleigh""s coefficient, for resolution, is given by the equation:       k    1    =            CD      xc3x97      NA        λ  
where CD is the critical dimension of the line feature, NA is the numerical aperture, and xcex is the wavelength of the exposure light. For example, if the exposure wavelength is 193 nanometers and the NA is 0.63, then k1 is 0.39. At such a low k1, extremely aggressive image enhancing techniques have to be used to produce usable images for IC manufacture. One such technique is the use of double exposures with two different masks.
For example, an alternating phase shifting mask (PSM) may be used when the desired feature size of an integrated circuit layer is on the same order of magnitude as the wavelength of light used in the photolithographic process. If a PSM is used, then a second exposure from a binary intensity mask (BIM) must be performed to remove any extra lines caused by the phase shifting interference at the feature boundaries.
In a typical photolithographic mask, layer features, or traces, are formed on the mask in an opaque material such as chrome. This chrome layer is formed overlying a transparent quartz substrate. Light is shown through this mask to expose a photosensitive material, commonly photoresist, as defined by the mask pattern. After the photoresist is developed, the photoresist will reflect a copy or a reverse copy of the mask pattern.
However, in a phase shifting mask, an additional component is added to the chrome and quartz system. Either through the application of an additional transparent layer or the through the removal of a portion of the quartz layer to a specific depth, the optical properties are changed in a part of the transparent (not covered by chrome) sections of the mask. Specifically, when light of the lithographic wavelength is shown through the mask, a phase shift is created between light waves that pass through the phase shifted area and the light waves that pass through the non-phase shifted area. By shifting the phase of the light by 180 degrees, nodes, or cancellations of energy will occur at opaque boundaries between the phase shifted and non-phase shifted areas. This principle is used to create more sharply defined boundary conditions during the photolithographic exposure. Sharper definition leads to improved pattern transfer.
In the case of the PSM method, two distinct reticles, the phase shifting mask (BIM) and binary intensity mask (BIM) are used. Referring now to FIG. 1, an alternating PSM mask 10 is shown for a simple feature. A chrome line 14 is formed on the mask. The chrome 14 is opaque and reflects exposure light away from the semiconductor wafer. The transparent regions of the mask 10 are divided into a zero degree, or non-phase shifting, region 18 and a 180 degree, or phase shifting, region 22. The phase shifting region 22 is specially treated to cause the transmitted exposure light to be shifted 180 degrees with respect to transmitted exposure light traveling through the non-phase shifting region 18.
Referring now to FIG. 2, the BIM mask 30 is illustrated. The purpose of the BIM mask 30 is to remove any extra lines caused by the interference of the phase shifted light and non-phase shifted light at the boundaries of each region. The BIM mask 30 contains a chrome feature 34 overlying the transparent substrate 38. The feature 34 is an appropriately oversized copy of the critical PSM feature of the PSM mask.
The PSM mask and the BIM mask are used sequentially. First, the semiconductor wafer is coated with a photoresist layer. Second, the PSM mask of FIG. 1 is loaded into the mask stage of the optical lithographic stepper and aligned. The photoresist layer is then exposed, field by field, to actinic light through the PSM mask. Third, the PSM mask is replaced with the BIM mask of FIG. 2. The BIM mask must be aligned. The undeveloped photoresist layer is exposed, field-by-field, to actinic light through the BIM layer. At the end of the process, every field has been exposed to thereby superimpose the patterns of the PSM mask and the BIM mask in every field.
Referring now to FIG. 3, a top view of the semiconductor substrate is shown. The photoresist layer 54 is developed. The photoresist layer 54 exhibits a very defined pattern overlying the semiconductor substrate 50. The double-exposure method enables the creation of smaller line widths than possible with a single, non-phase shifted exposure.
If a conventional stepper is used for this process, the operator must first install and then align the first mask. After exposing through the first mask, the operator must remove the first mask and install the second mask. This is because the conventional stepper can only hold and align a single mask at a time. The second mask must be aligned prior to the second exposure. It would be very advantageous and cost saving to eliminate a reticle change and alignment from the double-exposure process.
Several prior art approaches concern methods to double-expose an integrated circuit and apparatus for holding masks. U.S. Pat. No. 5,989,761 to Kawakubo et al teaches a method to expose photolithographic masks onto a substrate. First and second masks, corresponding to different substrate layers, are used. The first and second masks are exposed with different apparatus having different exposure field sizes. The first mask is exposed on the first apparatus. A perpendicular error and a mean value of rotation are detected for the first exposure. The second mask is rotated based on the detected error of the first mask to compensate and correct the error. U.S. Pat. No. 5,847,813 to Hirayanagi discloses a mask holding apparatus for lithographic exposure masks. The apparatus adds an inner frame to the conventional outer frame to thereby improve support, thermal transfer, and electrical grounding. U.S. Pat. No. 4,924,258 to Tsutsui teaches a mask holding and conveying mechanism. The mask holding mechanism comprises a reference member, an aperture, a spring-biased first member, and a spring-biased second member.
A principal object of the present invention is to provide an effective optical lithographic exposure apparatus and method of use thereof for patterning a photoresist layer in the manufacture of an integrated circuit device.
A further object of the present invention is to provide an exposure apparatus capable of holding two masks in a fixed relative position for sequential exposure of the mask patterns onto a semiconductor wafer.
A yet further object of the present invention is to provide an exposure apparatus capable of aligning two masks prior to the sequential exposure of the mask patterns onto a semiconductor wafer to thereby save time.
Another yet further object of the present invention is to provide an exposure apparatus capable of independently aligning two masks.
Another further object of the present invention is to provide an effective and very manufacturable method to pattern a photoresist layer wherein the photoresist layer is sequentially exposed to actinic light through two different masks.
Another yet further object of the present invention is to use a two mask holding apparatus to sequentially expose the photoresist layer through a PSM mask and through a BIM mask to thereby enhance the image of the pattern.
Another yet further object of the present invention is to expose sequentially the photoresist layer through the first mask and the second mask without a mask change and alignment to thereby save time.
In accordance with the objects of this invention, a new optical lithographic exposure apparatus is described. The apparatus may comprise step and scan capability. A wafer stage comprises a means of supporting a semiconductor wafer. A mask stage comprises a means of holding a first mask and a second mask and maintaining a fixed relative position between the first mask and the second mask. The mask stage may further comprise an independent means of aligning each mask. A light source comprises a means to selectively shine actinic light through either the first mask or the second mask. An imaging lens is capable of focusing the actinic light onto the semiconductor wafer. A means of stepping the mask stage across the semiconductor wafer is provided.
Also in accordance with the objects of the present invention, a new method to pattern a photoresist layer in the manufacture of an integrated circuit device is achieved. A photoresist layer is deposited overlying a semiconductor substrate. A first mask and a second mask are loaded into a mask stage of an optical lithographic exposure apparatus having a step and scan capability. The mask stage maintains a fixed relative position between the first mask and the second mask. The first mask and the second mask are aligned. The wafer is indexed to a starting field that becomes the current field. The first mask is scanned to expose the current field. The wafer is then indexed to a next field unexposed by the first mask. The stepping and scanning is repeated until every field on the semiconductor substrate is exposed with the first mask. The wafer is then indexed to the starting field that becomes the current field. The second mask is scanned to expose the current field. The wafer is then indexed to a next field unexposed by the second mask. The stepping and scanning is repeated until every field on the semiconductor substrate is exposed with the second mask. The patterns of the first mask and the second mask are thereby superimposed in every field. The photoresist layer is developed to thereby complete the patterning in the manufacture of the integrated circuit device.
Also in accordance with the objects of the present invention, a new method to pattern a photoresist layer in the manufacture of an integrated circuit device is achieved. A photoresist layer is deposited overlying a semiconductor substrate. A first mask and a second mask are loaded into a mask stage of an optical lithographic exposure apparatus having a step and scan capability. The mask stage maintains a fixed relative position between the first mask and the second mask. The first mask and the second mask are aligned. The wafer is indexed to a starting field that becomes the current field. The first mask is scanned to expose the current field. The second mask is scanned to expose the adjacent field. The wafer is stepped to a next field unexposed by the first mask. The stepping and scanning is repeated until every field on the semiconductor substrate is exposed. The wafer is indexed to the starting field. The wafer is then stepped to a next field unexposed by the second mask to become the current field. The second mask is scanned to expose the current field. The wafer is then indexed to the next field unexposed by the first mask to become the current field. The first mask is scanned to expose the current field. The stepping and scanning is repeated until every field on the semiconductor substrate is exposed. The patterns of the first mask and the second mask are thereby superimposed in every field. The photoresist layer is developed to thereby complete the patterning in the manufacture of the integrated circuit device.